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| preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 20651 rev: b amendment/ 0 issue date: january 1998 AM79C985 enhanced integrated multiport repeater plus (eimr+ ) distinctive characteristics n repeater functions compliant with ieee 802.3 repeater unit speci?ations n direct interface with the am79c987 hardware implemented management information base (himib ) device for building a basic managed multiport repeater n full software backwards compatibility with existing hub designs using integrated multiport repeater plus (imr+ )/himib devices n network management and optional feature accessibility through a dedicated serial management port n four integral 10base-t transceivers with on- chip ?tering eliminating the need for external ?ter modules on the 10base-t transmit-data (txd) and receive-data (rxd) lines n one reversible attachment unit interface (raui ) port used either as a standard ieee- compliant aui port for connection to a medium attachment unit (mau) or a reversed port for direct connection to a media access controller (mac) n low cost suitable for managed multiport repeater designs n number of repeater ports easily expandable with support for up to seven eimr+ devices without the need for an external arbiter n all ports capable of being individually isolated (partitioned) in response to excessive collision conditions or fault conditions n flexible led support for individual port status and network utilization leds n programmable extended distance mode on rxd lines allowing connection to cables longer than 100 meters n link test function and link test pulse transmission capable of being disabled through the management port allowing devices that do not implement the link test function to work with the eimr+ device n programmable automatic polarity detection and correction option permitting automatic recovery from wiring errors n full amplitude and timing regeneration for retransmitted waveforms n cmos device with a single +5-v supply general description the enhanced integrated multiport repeater plus (eimr+) device is a vlsi integrated circuit that pro- vides a system-level solution to designing managed multiport repeaters. the device integrates the repeater functions speci ed in section 9 of the ieee 802.3 standard and twisted pair transceiver functions com- plying with the 10base-t standard. the eimr+ device provides four twisted pair (tp) ports and one reversible aui (raui) port for direct connec- tion to a mac. the total number of ports per repeater unit can be increased by connecting multiple eimr+ devices through their expansion ports, hence, minimiz- ing the total cost per repeater port. the eimr+ device also provides a connection to the am79c987 himib device. the himib device monitors all the necessary counters, attributes, actions, and noti cations speci?d by ieee 802.3, section 19 (layer management for 10 megabit per second (mbps) baseband repeaters). when the eimr+ and himib devices are used together as a chip set, they provide a cost-effective solution to the problem of designing 10base-t basic managed multiport repeaters. the device is fabricated in cmos technology and requires a single +5-v supply.
2 AM79C985 preliminary block diagram . rx mux phase lock loop fifo fifo control preamble jam sequence partitioning link test timers aui port di ci do tp port 0 rxd txd rxd txd reset clock gen clk expansion port dat jam test and management port si_d so rst sclk amode rx mux tx mux eimr+ chip control tp port 3 manchester encoder manchester decoder col ack seli[ 1:0 ] selo led interface lda[4:0], ldb[4:0] ldga, ldgb ldc[2:0] act[7:0] str si crs_i crs 20651b-1 AM79C985 3 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list con?urations planned to be sup- ported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. device number/description AM79C985 enhanced integrated multiport repeater plus (eimr+) temperature range c = commercial (0?c to +70?c) alternate packaging option \w = trimmed and formed in a tray package type j = 84-pin plastic leaded chip carrier (pl 084) k = 100-pin plastic quad flat pack (pqr100) AM79C985 c j speed option not applicable \w valid combinations AM79C985 jc, kc\w 4 AM79C985 preliminary related products . part no. description am7990 local area network controller for ethernet (lance) am7992b serial interface adapter (sia) am7996 ieee 802.3/ethernet/cheapernet transceiver am79c90 cmos local area network controller for ethernet (c-lance) am79c98 twisted pair ethernet transceiver (tpex) am79c100 twisted pair ethernet transceiver plus (tpex+) am79c981 integrated multiport repeater plus (imr+ ) am79c982 basic integrated multiport repeater (bimr ) am79c983 integrated multiport repeater 2 (imr2 ) am79c984a enhanced integrated multiport repeater (eimr ) am79c987 hardware implemented management information base (himib ) am79c988 quad integrated ethernet transceiver (quiet ) am79c900 integrated local area communications controller (ilacc ) am79c940 media access controller for ethernet (mace ) am79c960 pcnet -isa single-chip ethernet controller (for isa bus) am79c961 pcnet -isa+ single-chip ethernet controller for isa (with microsoft?plug n play?support) am79c961a pcnet -isa ii full duplex single-chip ethernet controller for isa am79c965 pcnet -32 single-chip 32-bit ethernet controller am79c970 pcnet -pci single-chip ethernet controller (for pci bus) am79c970a pcnet -pci ii full duplex single-chip ethernet controller (for pci bus) am79c974 pcnet -scsi combination ethernet and scsi controller for pci systems AM79C985 5 preliminary table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 standard products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 related products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 connection diagrams (pl 084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 connection diagrams (pqr100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin designations (pl084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 listed by pin number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin designations (pqr100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 listed by pin number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 aui port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 twisted pair ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 expansion bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 management port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 basic repeater functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 repeater function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 signal regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 jabber lockup protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 collision handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 fragment extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 auto partitioning/reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 detailed functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 aui port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 tp port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 twisted pair transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 connection to alternate media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 twisted pair receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 link test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 polarity reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 visual status monitoring (led) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 network activity display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 expansion bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 internal arbitration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 imr+ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 management functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 eimr+ /himib interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 management port interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 command/response timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 port activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 management commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 set (write commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 get (read commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 systems applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 eimr+ to tp port connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 twisted pair transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 twisted pair receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 mac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 AM79C985 preliminary aui port interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 internal arbitration mode connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 imr+ mode external arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 eimr+ internal arbitration mode connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 imr+ mode external arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 visual status display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 dc characteristics over commercial operating ranges unless otherwise speci?d . . . . . . 35 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 key to switching waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 switching test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 appendix a - security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 AM79C985 7 preliminary connection diagrams (pl 084) 1 2 3 81 82 83 84 6 7 8 9 4 5 80 76 77 78 79 75 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 43 42 41 40 47 46 45 44 37 36 35 34 39 38 33 48 52 51 50 49 10 22 11 32 53 74 avss di+ di vdd ci+ ci avss do+ do amode str dvss crs_i si_d vdd rst clk dvss seli_0 seli_1 rext ldc2 ldc1 ldc0 vdd ldgb ldga ldb4 dvss lda4 ldb3 dvss ldb2 lda2 vdd ldb1 lda1 dvss ldb0 lda0 lda3 act7 txd3+ txd3 vdd vdd txd2+ txd2 avss rxd1+ rxd1 rxd2+ rxd2 rxd0+ rxd0 txd1 txd0+ txd0 avss txd1+ vdd rxd3+ rxd3 so si dvss act1 act0 vdd sclk vdd dat ack dvss crs jam act2 act5 act4 act3 dvss act6 col selo eimr+ AM79C985 20651b-2 8 AM79C985 preliminary connection diagrams (pqr100) 28 29 30 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 99 98 100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 81 83 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 eimr+ AM79C985 col dvss nc ack dat vdd jam crs dvss si so sclk vdd act0 act1 act2 dvss act3 act4 act5 vdd nc nc nc ldc2 ldc1 ldc0 vdd ldgb ldga ldb4 dvss lda4 ldb3 lda3 dvss ldb2 lda2 vdd ldb1 lda1 nc dvss ldb0 lda0 act7 nc nc nc act6 rxd3+ rxd2 nc rxd2+ rxd1 rxd1+ rxd0 rxd0+ vdd txd3 txd3+ avss txd2 txd2+ vdd txd1 txd1+ avss txd0 txd0+ rxd3 nc nc nc rext avss di+ di vdd ci+ ci avss do+ do amode str dvss crs_i si_d vdd rst nc clk dvss seli_0 seli_1 nc nc nc selo 20651b-3 AM79C985 9 preliminary logic symbol logic diagram do+ do di+ di ci+ ci sclk clk amode rst dv ss av ss txd+ txd rxd+ rxd v dd AM79C985 aui twisted pair ports (4 ports) jam dat ack col seli [1:0] selo expansion port test and management port si so led interface lda[4:0], ldb[4:0] ldga, ldgb ldc[2:0] act[7:0] str crs_i crs si_d 20651b-4 aui control port expansion port twisted pair port 0 twisted pair port 3 repeater state machine led port 20651b-5 10 AM79C985 preliminary pin designations (pl 084) listed by pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 txd3+ 22 amode 43 so 64 lda3 2 txd3- 23 str 44 sclk 65 ldb3 3 vdd 24 dvss 45 vdd 66 lda4 4 rxd0+ 25 crs_i 46 act0 67 dvss 5 rxd0- 26 si_d 47 act1 68 ldb4 6 rxd1+ 27 vdd 48 act2 69 ldga 7 rxd1- 28 rst 49 dvss 70 ldgb 8 rxd2+ 29 clk 50 act3 71 vdd 9 rxd2- 30 dvss 51 act4 72 ldc0 10 rxd3+ 31 seli_0 52 act5 73 ldc1 11 rxd3- 32 seli_1 53 act6 74 ldc2 12 rext 33 selo 54 act7 75 vdd 13 avss 34 col 55 lda0 76 txd0+ 14 di+ 35 dvss 56 ldb0 77 txd0- 15 di- 36 a ck 57 dvss 78 avss 16 vdd 37 dat 58 lda1 79 txd1+ 17 ci+ 38 vdd 59 ldb1 80 txd1- 18 ci- 39 jam 60 vdd 81 vdd 19 avss 40 crs 61 lda2 82 txd2+ 20 do+ 41 dvss 62 ldb2 83 txd2- 21 do- 42 si 63 dvss 84 avss AM79C985 11 preliminary pin designations (pqr100) listed by pin number note: 1. nc = no connection. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 rxd3- 26 seli_1 51 act6 76 ldc2 2 nc 27 nc 52 nc 77 nc 3 nc 28 nc 53 nc 78 nc 4 nc 29 nc 54 nc 79 nc 5 rext 30 selo 55 act7 80 vdd 6 avss 31 col 56 lda0 81 txd0+ 7 di+ 32 dvss 57 ldb0 82 txd0- 8 di- 33 nc 58 dvss 83 avss 9 vdd 34 a ck 59 nc 84 txd1+ 10 ci+ 35 dat 60 lda1 85 txd1- 11 ci- 36 vdd 61 ldb1 86 vdd 12 avss 37 jam 62 vdd 87 txd2+ 13 do+ 38 crs 63 lda2 88 txd2- 14 do- 39 dvss 64 ldb2 89 avss 15 amode 40 si 65 dvss 90 txd3+ 16 str 41 so 66 lda3 91 txd3- 17 dvss 42 sclk 67 ldb3 92 vdd 18 crs_i 43 vdd 68 lda4 93 rxd0+ 19 si_d 44 act0 69 dvss 94 rxd0- 20 vdd 45 act1 70 ldb4 95 rxd1+ 21 rst 46 act2 71 ldga 96 rxd1- 22 nc 47 dvss 72 ldgb 97 rxd2+ 23 clk 48 act3 73 vdd 98 nc 24 dvss 49 act4 74 ldc0 99 rxd2- 25 seli_0 50 act5 75 ldc1 100 rxd3+ 12 AM79C985 preliminary pin description aui port di+, di data in differential input di are differential, manchester receiver pins. the signals comply with ieee 802.3, section 7. do+, do data out differential output do are differential, manchester output driver pins. the signals comply with ieee 802.3, section 7. ci+, ci collision input differential input/output ci are differential, manchester i/o signals. as an input, ci is a collision-receive indicator. as an output, ci gen- erates a 10-mhz signal if the eimr+ device senses a collision. twisted pair ports txd+ 0-3 , txd 0-3 transmit data differential output txd are 10base-t port differential drivers (4 ports). rxd+ 0-3 , rxd 0-3 receive data differential input rxd are 10base-t port differential receive inputs (4 ports). expansion bus dat data input/output/3-state if the selo and a ck pins are asserted during non- collision conditions, the eimr+ device drives nrz data onto the dat line, regenerating the preamble if neces- sary. during a collision, when jam is high, dat is used to differentiate between single-port (dat=1) and multi- port (dat=0) collisions. dat is an output when a ck is asserted and the eimr+ device s ports are active; dat is an input when a ck is asserted and the ports are inactive. if a ck is not asserted, dat is in the high-im- pedance state. it is recommended that dat be pulled up or down via a high value resistor. jam jam input/output/3-state the active eimr+ device drives jam high, if it detects a collision condition on one or more of its ports. the state of the dat pin is used in conjunction with jam to indicate a single port (dat =1) or multiport (dat=0) col- lision. jam is in the high-impedance state if neither the sel nor a ck signal is asserted. it is recommended that jam be pulled up or down via a high value resistor. seli 0-1 select in input, active low when the expansion bus is con?ured for internal arbi- tration mode, these signals indicate that another eimr+ device is active; seli 0 or seli 1 is driven by selo from the upstream device. at reset, seli 0 selects between the internal arbitration mode and the imr+ mode of the expansion bus; a high selects the internal arbitration mode and a low selects the imr+ mode. selo select out output, active low if the expansion bus is con?ured for internal arbitration mode, an eimr+ device drives this pin low when it is active or when either of its seli 0-1 pins is low. an active eimr+ device is de?ed as having one or more ports receiving or colliding and/or is still transmitting data from the internal fifo, or extending a packet to the minimum of 96 bit times. when the expansion bus is con?ured for imr+ mode, selo is active when the eimr+ device is active (acquiring the functionality of the req pin on the am79c981 imr+ device). a ck acknowledge input/output, active low, open drain this signal is asserted to indicate that an eimr+ device is active. it also signals to the other eimr+ devices the presence of a valid collision status on the jam line and valid data on the dat line. when the eimr+ device is con?ured for internal arbitration mode, a ck is an i/o, and must be pulled to vdd via a minimum equivalent resistance of 1 k w. when the eimr+ device is con?ured for imr+ mode, a ck is an input driven by an external arbiter. col collision input/output, active low, open drain when asserted, col indicates that more than one eimr+ device is active. each eimr+ device generates the collision jam sequence independently. when the eimr+ device is con?ured for internal arbitration seli_1 seli_0 arbitration mode x 1 internal x 0 imr+ AM79C985 13 preliminary mode, col is an i/o and must be pulled to vdd via a minimum equivalent resistance of 1 k w. when the eimr+ device expansion port is con?ured for imr+ mode, col is an input driven by an external arbiter. management port amode aui mode input at reset, this pin sets the aui port to either normal or reversed mode. if amode is low at the rising edge of rst , the aui port is set to the normal mode; if amode is high, the aui port is set to the reversed mode. crs carrier sense output the states of the internal carrier-sense signals for the aui port and the four twisted-pair ports are output con- tinuously on this pin. the output is a serial bit stream synchronized to clk. when two eimr+ devices share a common himib device, crs on the ?st device must be connected to the crs_i (input) of the second eimr+ device. crs_i carrier sense in input crs_i is used when two eimr+ devices share a com- mon himib device. the crs output from the ?st eimr+ should be input to the second eimr+ via this pin. inter- nally, the second eimr+ appends the information on crs_i to its own carrier-sense information and outputs the combined result to the himib chip via its crs pin. at the rising edge of rst , crs_i is used to set the eimr+ device s management mode. crs_i high indi- cates that only a single eimr+ device is connected to the himib chip. crs_i low indicates that two eimr+ devices are connected to a himib chip. sclk serial clock in input serial data (input or output) is clocked (in or out) on the rising edge of the signal on this pin. sclk is asynchro- nous to clk and can operate at frequencies up to 10 mhz. si serial in input the si pin is used as a test/management serial input port. management commands are clocked in on this pin synchronous to the sclk input. at reset, si sets the state of the automatic polarity re- versal function. if si is high at the rising edge of rst , automatic polarity reversal is disabled. if si is low at the rising edge of rst , automatic polarity reversal is enabled. si_d serial input append input si_d is used when two eimr+ devices share a common himib device. the so output from the ?st eimr+ de- vice should be input to the second eimr+ chip via this pin. internally, the second eimr+ chip appends the si_d data to its own serial data stream and outputs the result to the himib device via its so pin. when two eimr+ devices are connected to a himib device, the himib device has attribute counters for the aui port on only one of the eimr+ devices. that eimr+ device is referred to as the primary eimr+ device. the other device is referred to as the secondary eimr+ de- vice. at the rising edge of rst , the combination of crs_i and si_d is used to set the eimr+ device s manage- ment mode. if crs_i is high, the state of si_d is ig- nored and the eimr+ device is con?ured as a single eimr+. if crs_i is low, si_d high indicates that the eimr+ device is the secondary device. if crs_i is low and si_d is low, the eimr+ device is con?ured as the primary device. so serial out output the so pin is used as a management command serial output port. responses to management commands are clocked out on this pin synchronous to the sclk input. str store input the himib device uses this input to communicate with the eimr+ device. str connects to an internal pull-up resistor. the resistance value is suf?iently high to allow the str pins of two eimr+ devices to be connected together without presenting an excessive load to the himib device. two eimr+ devices crs_i si_d single eimr+ device primary eimr+ device secondary eimr+ device 0 0 ? 0 1 ? 1 0 ? 1 1 ? 14 AM79C985 preliminary led interface lda 0-4 , ldb 0-4 led drivers output, open drain lda 0-4 and ldb 0-4 drive led bank a and led bank b, respectively. lda 0 and ldb 0 indicate the status of the aui port; lda 1-4 and ldb 1-4 indicate the status of the four tp ports. the port attributes monitored by lda 0-4 and ldb 0-4 are programmed by three pins, ldc 0-2 . ldga global led driver, bank a output, open drain ldga is the global led driver for led bank a. the signal represents global crs or col conditions. in a multiple-eimr+ con?uration, ldga from each of the eimr+ devices can be tied together to drive a single global led in bank a. ldgb global led driver, bank b output, open drain ldgb is the global led driver for led bank b. the signal represents global crs or jab conditions. in a multiple eimr+ con?uration, ldgb from each of the eimr+ devices can be tied together to drive a single global led in bank b. ldc 0-2 led control input these pins select the attributes that will be displayed on lda 0-4 , ldb 0-4 , ldga, and ldgb. if an led is pro- grammed to display two attributes, the attribute associ- ated with the periodic blink takes precedence. act 0-7 activity display output, open drain these signals drive the activity leds, which indicate the percentage of network utilization. the display is up- dated every 250 ms. miscellaneous pins rst reset input, active low when rst is low, the eimr+ device resets to its de- fault state. on the rising (trailing) edge of rst , the eimr+ also monitors the state of the sel i 0-1 , si, and amode pins, to con?ure the operating mode of the device. in multiple eimr+ systems, the falling (leading) edge of the rst signal must be synchronized to clk. clk master clock in input this pin is a 20-mhz clock input. rext external reference input this pin is used for an internal current reference. it must be tied to vdd via a 13-k w resistor with 1% tolerance. vdd power power pin this pin supplies power to the device. avss analog ground ground pin this pin is the ground reference for the differential receivers and drivers. dvss digital ground ground pin this pin is the ground reference for all the digital logic in the eimr+ device. AM79C985 15 preliminary functional description the AM79C985 eimr+ device is a single-chip imple- mentation of an ieee 802.3/ethernet repeater (or hub). it is offered with four integral 10base-t ports plus one raui port comprising the basic repeater. the eimr+ device is also expandable, enabling the implementation of high port count repeaters based on several eimr+ devices. the eimr+ device interfaces directly with amd s am79c987 himib device. this allows hardware de- signers to implement a fully managed multiport re- peater, as speci?d by the ieee 802.3 standard, section 19, layer management for 10 mbps baseband repeaters . when the eimr+ and himib devices are used as a chip set, the himib device maintains com- plete repeater and per-port statistics, which can be ac- cessed on demand through an 8-bit parallel interface. the eimr+ chip complies with the full set of repeater basic functions as de?ed in section 9 of iso 8802.3 (ansi/ieee 802.3c). the basic repeater functions are summarized in the paragraphs below. basic repeater functions the AM79C985 chip implements the basic repeater functions as de?ed by section 9.5 of the ansi/ieee 802.3 speci?ation. repeater function if any single network port senses the start of a valid packet on its receive lines, the eimr+ device will re- transmit the received data to all other enabled network ports (except when contention exists among any of the ports or when the receive port is partitioned). to allow multiple eimr+ device con?urations, the data will also be repeated on the expansion bus data line (dat). signal regeneration when retransmitting a packet, the eimr+ device en- sures that the outgoing packet complies with the ieee 802.3 speci?ation in terms of preamble structure and timing characteristics. speci?ally, data packets re- peated by the eimr+ device will contain a minimum of 56 preamble bits before the start-of-frame delimiter. in addition, the eimr+ restores the voltage amplitude of the repeated waveform to levels speci?d in the ieee 802.3 speci?ation. finally, the eimr+ device restores signal symmetry to repeated data packets, removing jit- ter and distortion caused by the network cabling. jitter present at the output of the aui port will be better than 0.5 ns; jitter at the tp outputs will be better than 1.5 ns. the start-of-packet propagation delay for a repeater set is the time delay between the ?st edge transition of a data packet on its input port to the ?st edge transition of the repeated packet on its output ports. the start-of- packet propagation delay for the eimr+ is within the speci?ation given in section 9.5.5.1 of the ieee 802.3 standard. jabber lockup protection the eimr+ device implements a built-in jabber protec- tion scheme to ensure that the network is not disabled by the transmission of excessively long data packets. this protection scheme causes the eimr+ device to in- terrupt transmission for 96 bit-times if the device has been transmitting continuously for more than 65,536 bit times. this is referred to as mau jabber lockup pro- tection (mjlp). the mjlp status for the eimr+ device can be read through the management port, using the get mjlp status command. collision handling the eimr+ device will detect and respond to collision conditions as speci?d in the ieee 802.3 speci?ation. repeater con?urations consisting of multiple eimr+ devices also comply with the ieee 802.3 speci?ation, using status signals provided by the expansion bus. in particular, a repeater based on one or more eimr+ de- vices will handle the transmit collision and one-port-left collision conditions correctly, as speci?d in section 9 of the ieee 802.3 speci?ation. fragment extension if the total packet length received is less than 96 bits, including preamble, the eimr+ device will extend the repeated packet length to 96 bits by appending a jam sequence to the original fragment. auto partitioning/reconnection any of the tp ports or the aui port can be partitioned if the duration or frequency of collisions becomes exces- sive. the eimr+ device will continue to transmit data packets to a partitioned port, but will not respond, as a repeater, to activity on the partitioned port s receiver. the eimr+ device will monitor the port and reconnect it once certain criteria are met. the criteria for recon- nection are speci ed by the ieee 802.3 standard. in addition to the standard reconnection algorithm, the eimr+ device implements an alternative reconnection algorithm, which provides a more robust partitioning function for the tp ports and/or aui port. the eimr+ device partitions each tp port and the aui port sepa- rately and independently of other network ports. the eimr+ device will partition an enabled network port if either of the following conditions occurs at that port: 1. a collision condition exists continuously for more than 2048 bit times. (aui port?qe signal active; tp port?imultaneous transmit and receive). 2. a collision condition occurs during each of 32 con- secutive attempts to transmit to that port. in the aui port, a collision condition is indicated by an active sqe signal. in a tp port, a collision condition is 16 AM79C985 preliminary indicated when the port is simultaneously attempting to transmit and receive. once a network port is partitioned, the eimr+ device will reconnect that port, according to the selected re- connection algorithm, as follows: 1. standard reconnection algorithm? data packet longer than 512-bit times (nominal) is transmitted or received by the partitioned port without a collision. 2. alternative reconnection algorithm? data packet longer than 512-bit times (nominal) is transmitted by the partitioned port without a collision. a partitioned port can also be reconnected by disabling and re-enabling the port. all tp ports use the same reconnection algorithm; ei- ther they must all use the standard algorithm, or they must all use the alternative reconnection algorithm. however, the reconnection algorithm for the aui port is programmed independently from that of the tp ports. detailed functions reset the eimr+ device enters the reset state when the reset (rst ) pin is driven low. after the initial applica- tion of power, the rst pin must be held low for a min- imum of 150 m s. if the rst pin is subsequently asserted while power is maintained to the eimr+ de- vice, a reset duration of only 4 m s is required. this al- lows the eimr+ device to reset its internal logic. during reset, the eimr+ registers are set to their default val- ues. also during reset, the eimr+ device sets the out- put signals to their inactive state; that is, all analog outputs are placed in their idle state, no bidirectional signals are driven, all active-high signals are driven low and all active-low signals are driven high. in a multiple eimr+ system, the reset signal must be syn- chronized to clk. see figure 13 in the systems appli- cations section. the eimr+ device also monitors the state of the sel i 0-1 , si, crs_i, si_d, and amode pins on the ris- ing (trailing) edge of rst to con?ure the operating mode of the device. table 1 summarizes the state of the eimr+ chip follow- ing reset. aui port the aui port is fully compatible with the ieee 802.3, section 7 requirement for an aui port. it has the signals associated with an aui port: do, di, and ci. the aui port has two modes of operation: normal and reverse. when con?ured for normal operation, the functionality is that of an aui port on a mac (ci is an input). when con?ured for reverse operation, the func- tionality is that of an aui on a mau (ci is an output). the mode of the aui port is set during the trailing (ris- ing) edge of the reset pulse, by the state of the amode pin. a low sets the aui port to its normal mode (ci in- put) and a high sets the aui port to its reverse (ci out- put) mode. the eimr+ device can be connected directly to a mac through the aui port. this requires that the aui port be con?ured for reverse operation. refer to the systems applications section for more details. tp port interface twisted pair transmitters txd is a differential twisted-pair driver. when properly terminated, txd will meet the electrical requirements for 10base-t transmitters as speci?d in ieee 802.3, section 14.3.1.2. the txd signal is ?tered on the chip to reduce har- monic content per ieee 802.3, section 14.3.2.1 (10base-t). since ?tering is performed in silicon, txd can connect directly to a standard transformer, thereby, eliminating the need for external ?tering modules. proper termination is shown in the systems applica- tions section. table 1. eimr+ states after reset function state after reset pull up/pull down active-low outputs high no active-high outputs low no so output high no dat, jam high impedance either transmitters (tp and aui) idle no receivers (tp and aui) enabled terminated aui partitioning/reconnection algorithm standard algorithm n/a tp partitioning/reconnection algorithm standard algorithm n/a link test functions for tp ports enabled, tp ports in link fail n/a automatic receiver polarity reversal function disabled if si pin is high enabled if si pin is low n/a AM79C985 17 preliminary connection to alternate media the eimr+ device can be connected to the aui port of any mau device. thus, it can support 10base-2, 10base-5, and 10base-fl. to connect to an alternate media type, on-chip ?tering should be disabled. this can be achieved by substituting the normal 110- w re- sistor connected across the txd differential output with a 500- w resistor. if on-chip ?tering is disabled at a tp port, the link pulse must also be disabled. refer to the section on eimr+ management commands for pro- gramming details. once port ?tering is disabled, the txd output will be a square waveform and can be connected to the aui port of a transceiver. some external components are nec- essary to correctly interface the txd output to the trans- ceiver. twisted pair receivers rxd is a differential twisted-pair receiver. when prop- erly terminated, rxd will meet the electrical require- ments for 10base-t receivers as speci?d in ieee 802.3, section 14.3.1.3. the receivers do not require external ?ter modules. proper termination is shown in the systems applications section. the receiver s threshold voltage can be programmed to an extended-distance mode. in this mode, the differen- tial receiver s threshold is reduced to allow a longer cable than the 100 meters speci?d in the ieee 802.3 standard. for programming details, refer to the man- agement commands section. link test the integrated tp ports implement the link test func- tion, as speci?d in the ieee 802.3 10base-t stan- dard. the eimr+ device will transmit link test pulses to any tp port after that port s transmitter has been in- active for more than 8 ms to 17 ms. conversely, if a tp port does not receive any data packets or link test pulses for more than 65 ms to 132 ms and the link test function is enabled for that port, then that port will enter the link-fail state. the eimr+ device will disable a port in link-fail state (i.e., disable repeater transmit and re- ceive functions) until it receives either four consecutive link test pulses or a data packet. the link test function can be disabled via the eimr+ management port on a port-by-port basis, to allow the eimr+ device to operate with pre-10base-t networks that do not implement the link test function. when the link test function is disabled, the eimr+ device will not allow the tp port to enter link-fail state, even if no link test pulses or data packets are being received. note, however, that the eimr+ device will always transmit link test pulses to all tp ports, regardless of whether or not the port is enabled, partitioned, in link-fail state, or has its link test function disabled. separate man- agement commands exist for enabling and disabling the transmission of link test pulses on a port-by-port basis. polarity reversal the tp ports can be programmed to receive data if a wiring error results in a data packet being received at a tp port with reversed polarity. this function will be en- abled upon reception of a negative end transmit delim- iter (etd) or negative pulses and allows subsequent packets to be received with the correct polarity. the po- larity-reversal function is executed once following reset or link-fail and can be programmed via the manage- ment port to be enabled or disabled on a port-by-port basis. the function may be enabled or disabled, follow- ing a reset, depending on the level of the si signal on the rising edge of the rst pulse. visual status monitoring (led) support the eimr+ status port can be connected to leds to facilitate the visual monitoring of repeater port status. the status port has twelve output signals, lda 0-4 , and ldb 0-4 , ldga, and ldgb. lda 0-4 and ldb 0-4 repre- sent the four tp ports and aui port. ldga and ldgb are global indicators. attributes that may be monitored are carrier sense (crs), collision (col), partition (par), link status (link), loopback (lb), port dis- abled (dis), and jabber (jab). three control bits, ldc 0-2 , select the particular attributes to be displayed on the leds. table 1 shows how the programming combinations for ldc 0-2 control the attributes that will be monitored. each led drive pin (ldga, ldgb, lda 0-4 , and ldb 0-4 ) has two states: off and low. when none of the se- lected attributes are true, the driver is off and the diode is unlit. when an attribute is true, the driver is low, and the corresponding leds in bank a or bank b will be lit. some of the settings (ldc 2 = 1) include a blink func- tion. this allows two attributes to be selected for a given state on the pin. as an example when ldc 0-2 = 110, the lda outputs relating to tp ports will be solidly lit when there is a link established at that port. however, whenever there is activity on a port, the corresponding lda pin will switch on (low) and off at a period of 130 ms. note that a partition on that port will also cause the pin to go low. on ldc settings that have two attributes for a state on a pin (blink or solid-on), the attribute causing the output to blink has priority. (those attributes are shown in table 2 with a blink period speci?d next to it.) if an at- tribute has no blink period speci?d, the led indicates the attribute by being solidly lit. 18 AM79C985 preliminary notes: 1. crs = carrier sense, col = collision, jab = jabber, link = link, lb = loop back, par = partition, dis = port disabled, blk = blink (number = period of blink). 2. for the ldc 0-2 setting of 000: if the port is partitioned, the link led is off. 3. all leds blink 16 times at 260 ms per blink after reset. 4. all leds are on for approximately 4 seconds after reset. 5. ldc 0-2 = ?010? and ?011? are undetned. the leds can also be controlled via the management port. the enable software override commands turn the leds on regardless of the attributes selected for display through the ldc setting. enable software override of bank a leds causes the lda 0-4 and ldga pins to be driven low, and enable software override of bank b leds causes the ldb 0-4 and ldgb pins to be driven low. the blink rate is set by the software override led blink rate command. the periods are off, 512 ms, 1560 ms, or solid on. led software override is executed in two stages, by trst issuing the blink rate (software override of led blink rate) and then issuing the command to enable the particular port leds (enable software override of bank a/b leds). all port combinations selected for software override control will reference the blink rate last issued by the software override of the led blink rate command. lda 0-4 , ldb 0-4 , ldga, and ldgb are open drain out- put drivers that sink 12 ma of current to turn on the leds. in a multiple eimr+ contguration, the outputs from the global led drivers (ldga and ldgb) of each chip can be tied together to drive a single pair of global status leds. crs and col are extended to make it easier for visual recognition; that is, they will remain active for some time even if the corresponding condition has expired. once carrier sense is active, crs will remain active for a minimum of 4 ms. once a collision is detected, col is active for at least 4 ms. the exception to this rule is for selection ldc 0-2 = 111. for this selection, col is stretched to 100 m s. when ldc 0-2 = 000 or ldc 0-2 = 001, the loopback at- tribute (lb) for the aui port is displayed on lda 0 . lb is true when do on the mau is successfully looped back to di on the aui port. lb is false (off) if a loopback error is detected, or if the aui port is disabled or in the re- verse mode. transmit carrier sense is sampled at the end of packet to determine the state of lb. the state of lb remains latched until carrier sense is sampled again for the next packet. the default/power-up state for lb is false (off). figure 1 shows the recommended connection of leds. when lda 0-4 , ldb 0-4 , ldga, or ldgb are low, the led lights. figure 1. visual monitoring application?direct led drive table 2. led attribute-monitoring program options led control global leds tp leds aui leds ldc 2 ldc 1 ldc 0 ldga ldgb lda 1-4 ldb 1-4 lda 0 ldb 0 0 0 0 crs col link (note 2) par lb par 0 0 1 crs col link crs lb crs 0 1 0 reserved (note 5) 0 1 1 reserved (note 5) 1 0 0 crs 260-ms blk col 260-ms blk link crs 260-ms blk par col 260-ms blk crs 260-ms blk par col 260-ms blk 1 0 1 col jab link (note 3) crs 512-ms blk par (note 3) (note 3) crs 512-ms blk par (note 3) 1 1 0 crs col link crs 130-ms blk par or dis crs 130-ms blk par or dis 1 1 1 crs col link (note 4) par 1.56-s blk col (note 4) (note 4) par 1.56-s blk par (note 4) eimr+ led interface lda[4:0] ldb[4:0] ldga ldgb r v dd typical 20651a-6 20651b - 6 AM79C985 19 preliminary network activity display the eimr+ status port can drive up to eight leds to in- dicate the network-utilization level as a percentage of bandwidth. the status port uses eight dedicated out- puts (act 0-7 ) to drive a series of leds. the number of leds in the series that will be lit increases as the amount of network activity increases. act 0 represents the lowest level of activity; act 7 represents the high- est. act 0-7 are open-drain outputs that typically sink 12 ma of current to turn on the leds. see figure 2. table 3 shows act 0-7 as a function of the percentage of network utilization. the table uses a scale that is more sensitive at low utilization levels. 100% utilization represents the maximum number of events that could occur in a given window of time. the update rate and corresponding internal sampling window for act[7:0] is 250 ms. during this sampling window, a counter is used to count the number of times repeater transmit activity is true. the counter uses a free-running clock which has the granularity to detect the minimum packet size of 96 bit times. figure 3 shows the timing relationship between the sampling window, counting clock, and transmit activity. figure 2. network activity display . figure 3. activity sampling table 3. network utilization number of leds lit by act 0-7 percentage utilization 8 >80% 7 >64% 6 >32% 5 >16% 4 >8% 3 >4% 2 >2% 1 >1% act[0] act[1] act[4] act[5] act[2] act[3] act[6] act[7] eimr+ led interface v dd 20651a-7 20651b-7 sampling window counting clock xmit activity counter is active next counting cycle latch data; update display; clear counter 20651b-8 20 AM79C985 preliminary expansion bus interface the eimr+ device expansion bus allows multiple eimr+ devices to be interconnected. the expansion bus supports two modes of operation: internal arbitration mode and imr+ mode. the internal arbitration mode uses a modi?d daisy-chain scheme to eliminate the need for any external arbitration cir- cuitry. the imr+ mode maintains the full functionality of the imr+ (am79c981) expansion bus and bene?s from minimum delays. in this mode, the eimr+ device requires external circuitry to handle arbitration for con- trol of the bus. the eimr+ arbitration mode is determined at reset. this occurs on the trailing edge of rst according to the state of seli 0-1 , as illustrated in figure 4. the eimr+ device can be connected to a himib device, as described in the eimr+/himib interconnection sec- tion. the connection to a himib device is not dependent on the mode of the expansion bus. in other words, the eimr+ device can be connected to a himib device whether the expansion bus is in internal-arbitration mode or imr+ mode. internal arbitration mode the internal arbitration mode uses a daisy-chain (cas- cade) con?uration. seli 0-1 are arbitration inputs and selo is the arbitration output. selo goes low when there is activity on one or more of the eimr+ ports, or a seli input is low. the sel lines are connected as shown in figure 5. this technique allows activity indica- tion to propagate down the chain to the end device. all unused seli inputs must be tied to vdd. a ck and col are global activity i/o pins. when the eimr+ device senses activity, it drives a ck low. figure 4. expansion bus mode selection an eimr+ device drives col low when it senses more than one device is active; that is, if the device has an active port and a seli input is low, or both seli inputs are low. in boolean notation, the formula for col is as follows: col = (active port & (seli 1 + seli 0 ))+ (seli 1 & seli 0 ) where & represents the boolean and operation + represents the boolean or operation a ck and col are mutually exclusive. if the eimr+ de- vice driving a ck senses col low, the device will deassert a ck. dat and jam are synchronized to clk. dat is the rep- etition of data from any connected port (either tp or aui port) encoded in nrz format. jam is an internal collision indicator. if jam is high, the active eimr+ de- vice has detected an internal collision across one or more of its ports. when this occurs, the dat signal dis- tinguishes between single-port collisions and multiport collisions. dat = 1 indicates a single port collision; dat = 0 indicates a multiport collision. the drive capabilities of the i/o signals on the expan- sion bus (dat, jam, a ck , and col ) are suf?ient to allow seven eimr+ devices to be connected together without the use of external transceivers or buffers. the maximum number of eimr+ devices that can be daisy chained is limited by the propagation delay of the eimr+ devices. in practice, the depth of the cascade is limited to three eimr+ devices, thus allowing a maxi- mum of seven eimr+ devices connected together via this expansion bus as shown in figure 5. the active device will not drive the data line, dat, until one bit time (100 ns) after selo goes low. this is to avoid a situation where two devices drive dat simultaneously. imr+ mode in imr+ mode, the expansion bus requires an external arbiter. the arbiter allows only one eimr+ device to control the expansion bus. if more than one device at- tempts to take control, the arbiter terminates all access and signals a collision condition. in imr+ mode, dat and jam retain the same function- ality as in internal arbitration mode, but a ck and col are inputs to the eimr+ device, driven by the external arbiter. the arbiter should drive a ck low when ex- actly one eimr+ device is active. it should drive col when more than one eimr+ device is active. selo is an output from the eimr+ device. it indicates that the eimr+ device has an active port and is requesting ac- cess to the bus. when a ck is high, dat and jam are in the high-impedance state. dat and jam go active when a ck goes low. refer to the systems applica- tions section (fig.14) for the con?uration of imr+ mode of operation. note: the imr+ mode is recommended when arbitrating between multiple boards. rst seli_0 mode selection seli_1 seli_0 arbitration mode x 1 internal x 0 imr+ 20651b-9 AM79C985 21 preliminary figure 5. internal arbitration?imr+ devices in cascade management functions the eimr+ device receives management commands in the form of byte-length data on the serial input pin, si. if the eimr+ device is expected to provide data in response to the command, it will send byte-length data to the serial-output pin, so. both the input and output data streams are clocked with the rising edge of the sclk signal. the byte-length data is in rs232 serial- data format; that is, one start bit followed by eight data bits. the externally generated clock at the sclk pin may be either a free-running clock synchronized to the input bit patterns, or a series of individual transitions meeting the setup-and-hold times with respect to the input bit pattern. if the latter method is used, 20 sclk clock transitions are required for management com- mands that produce so data, and 14 sclk clock tran- sitions are required for management commands that do not produce so data. v dd 1k w seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col 20651b-10 22 AM79C985 preliminary eimr+/himib interconnection the eimr+ device interfaces directly to the himib de- vice for full repeater manageability. to this end, the eimr+ device has a management port and a serial out- put that allows the himib device to monitor port activity. the eimr+ device is designed to allow one or two eimr+ devices to operate with a single himib device. because the himib device can monitor nine ports (8 tp ports & 1 aui port), one of the eimr+ aui ports is not managed (statistics not kept). when two eimr+ devices are connected to a himib device, one is designated the primary device and the other is designated the second- ary device. this designation serves to identify which device has the managed aui port. the primary device has the managed aui port and tp4-7. the secondary device has the unmanaged aui port and tp0-3. figure 6 shows how the himib and eimr+ devices are inter- connected. when only one eimr+ device is connected to a himib device, the aui port is managed. the himib device treats the twisted-pair ports as tp0-3. although the himib device does not monitor the aui port on the secondary eimr+ device, the aui port on the secondary device defaults to enabled at reset. the port can be disabled via the secondary aui port enable command. management port interface the eimr+ management port is made up of six signals: si, si_d, so, crs, crs_i, and sclk. si is the serial input from an external management module or the himib device. on the secondary eimr+ device, si_d is the response input from the primary eimr+ device. it is also used at reset to set the eimr+ device as either a primary or secondary device. crs transmits the state of the eimr+ device s internal carrier sense signals. figure 6. eimr-to-himib connection aui u port & tp[3:0] crs_i si_d crs so eimr+ (secondary) sclk si aui m port & tp[7:4] crs_i si_d crs so eimr+ (primary) sclk si sclk si so crs himib b) two eimr devices connected to a himib aui m port & tp[3:0] crs_i si_d crs so eimr+ sclk si sclk si so crs himib a) one eimr device connected to a himib v dd dv ss 20651b-11 AM79C985 23 preliminary when two eimr+ devices are connected to one himib device, the secondary device transmits the status of its tp ports, then transmits the status of the primary eimr+ tp ports and aui port (crs and ci). note that the sec- ondary device does not transmit the status of its aui port. at reset, the secondary device (and single eimr+ device) internally synchronizes the crs stream to begin with the aui ci bit. so is the eimr+ device response to a get command. the pins si_d and crs_i are multi-purpose pins. their primary purpose is management input to the primary eimr+ device. they are also used to set the manage- ment mode of the eimr+ device. the mode is set on the rising edge of rst . the settings are shown in table 4. following reset, the eimr+ devices retain their manage- ment designations. however, crs_i and si_d return to their management port functions. command/response timing figure 7 shows the command/response timing. at the end of a get command, the eimr+ device waits two sclk cycles and then transmits the response on so. the secondary eimr+ device stores the data received on the si_d input (from the primary eimr+ device) in an internal register. when it has transmitted d3 data, it appends the received response to the end of the so signal. following reset, after the eimr+ devices have been as- signed their primary and secondary designation, so and si_d return to their management-port functions. port activity in addition to providing a means for receiving com- mands and sending data in response to those com- mands, the management port includes a crs signal that transmits the state of the eimr+ device s internal carrier-sense signals. when two eimr+ devices are connected to one am79c987 himib device (as shown in the system applications section), crs_i of the secondary device receives the following signals from the primary device: the carrier-sense signals of the aui port, the ci-bit sta- tus of the aui port, and the carrier-sense signals of the tp ports. the secondary device transmits the status of the aui port (crs and ci) for the primary device, the status of its own tp ports (tp0-tp3), and then the sta- tus of the primary device s tp ports (tp4-tp7). the status of the aui port of the secondary device is not retransmitted (see figure 8). figure 7. management get command/response table 4. eimr+ device management designations two eimr+ devices crs_i si_d single eimr+ device primary eimr+ device secondary eimr+ device 0 0 ? 0 1 ? 1 0 ? 1 1 ? note: for so on the primary device, d[3:0] corresponds to tp[7:4]. st d0 d1 d2 d3 d4 d5 d6 d7 st d0 d1 d2 d3 sclk si so primary eimr+ device or single eimr+ device st d0 d1 d2 d3 d4 d5 d6 d7 so secondary eimr+ device 20651b-12 24 AM79C985 preliminary figure 8. port activity signals with am79c987 himib device management commands the following section details the operation of each management commands available in the eimr+ de- vice. in all cases, the individual bits in each command are shown with the most-signi?ant bit (bit 7) on the left and the least-signi?ant bit (bit 0) on the right. table 5 and table 6 show a summary of default states and a summary of management commands, respectively. note: data is transmitted and received on the serial data lines least-signi?ant bit ?st and most-signi?ant bit last. crs one eimr+ device cp t0 t1 t2 t3 t4 t5 t6 t7 cp t4 t5 t6 t7 c a t0 t1 t2 t3 tclk crs secondary crs primary* ap ap clk * shows actual output stream to secondary device. 20651b-13 table 5. summary of default states after reset eimr+ programmable option csa off aui partitioning algorithm normal tp partitioning algorithm normal aui/tp port enabled link test enabled link pulse enabled automatic receiver polarity reversal state of si at reset extended distance mode disabled blink rate off software override of leds disabled AM79C985 25 preliminary table 6. management port command summary commands si data so data single eimr+ device so data primary so data secondary set (write commands) eimr+ chip programmable options 0000 1csa alternate aui partitioning algorithm 0001 1111 alternate tp partitioning algorithm 0001 0000 primary aui port disable 0010 1111 secondary aui port disable 0010 1110 primary aui port enable 0011 1111 secondary aui port enable 0011 1110 tp port disable 0010 0### tp port enable 0011 0### disable link test function (per tp port) 0100 0### enable link test function (per tp port) 0101 0### disable link pulse (per tp port) 0100 1### enable link pulse (per tp port) 0101 1### disable automatic receiver polarity reversal (per tp port) 0110 0### enable automatic receiver polarity reversal (per tp port) 0111 0### disable receiver extended distance mode (per tp port) 0110 1### enable receiver extended distance mode (per tp port) 0111 1### disable software override of leds (per port - aui & tp) 1001 #### enable software override of bank-a leds (per port - aui & tp, global) 1011 #### enable software override of bank-b leds (per port - aui & tp, global) 1100 #### software override led blink rate 1110 1### get (read commands) aui port status (b, s, and l cleared) 1000 1111 pbsl 0000 0000 pbsl pbsl p pbsl s aui port status (b cleared) 1000 1101 pbsl 0000 0000 pbsl pbsl p pbsl s aui port status (s, l, cleared) 1000 1011 pbsl 0000 0000 pbsl pbsl p pbsl s aui port status (none cleared) 1000 1001 pbsl 0000 0000 pbsl pbsl p pbsl s tp port partitioning status 1000 0000 0000 c3..c0 0000 c7..c4 c7..c0 bit rate error status of tp ports 1010 0000 0000 e3..e0 0000 e7..e4 e7..e0 link test status of tp ports 1101 0000 0000 l3..l0 0000 l7..l4 l7..l0 receive polarity status of tp ports 1110 0000 0000 p3..p0 0000 p7..p4 p7..p0 mjlp status 1111 0000 m000 0000 0000 m000 m p 000 m s 000 version 1111 1111 0000 0011 0000 0011 0011 p 0011 s 26 AM79C985 preliminary set (write commands) chip prog r ammab le options si data 0000 1csa so data (pri) none so data (sec) none the eimr+ chip programmable options can be enabled (or disabled) by setting (or resetting) one or more of the c, s, and a bits in the command string. the three pro- grammable options are c - ci reporting, s - aui test mask, and a - alternate port activity monitor (pam) function. c himib connection this bit, when set, indicates to the eimr+ device that it is connected to a himib device. s aui sqe test mask setting this bit allows the eimr+ chip to ignore activity on the ci signal pair, during the sqe test window, fol- lowing a transmission on the aui port. enabling this function does not prevent the reporting of this condi- tion by the eimr+ device. the two functions operate independently. the sqe test window, as de?ed in ieee 802.3 (sec- tion 7.2.2.2.4) is from 6 bit times to 34 bit times (0.6 m s to 3.4 m s). this includes the delay introduced by a 50- m aui. ci activity that occurs outside this window is not ignored and is treated as a true collision. a alternate port activity monitor function setting this bit causes the port activity monitor (pam) function to be altered such that the crs data is pre- sented unmodi ed. in default operation, crs is masked if the port is either disabled or partitioned. note that the himib device resets this bit (default operation). alter nate a ui p ar titioning algor ithm si data 0001 1111 so data (pri) none so data (sec) none invoking this command sets the partition/reconnection scheme for the aui port to the alternate (transmit-only) reconnection algorithm. to return the aui port to the standard (transmit or receive) reconnection algorithm, it is necessary to reset the eimr+ device. the standard partitioning algorithm is selected on reset. if two eimr+ devices are connected, this command sets both aui ports. alter nate tp p ar titioning algor ithm si data 0001 0000 so data (pri) none so data (sec) none invoking this command sets the partition/reconnection scheme for the tp ports to the alternate (transmit-only) reconnection algorithm. to return the tp ports to the standard (transmit or receive) reconnection algorithm, it is necessary to reset the eimr+ device. the standard partitioning algorithm is selected on reset. pr imar y a ui p or t disab le si 0010 1111 so data (pri) none so data (sec) none this command disables the aui port on the primary eimr+ device. subsequently the eimr+ chip will ig- nore all inputs to this port and will not transmit a dat or jam pattern on the aui port. disabling the aui port also sets the partitioning state machine of the aui port to the idle state. therefore, a partitioned port can be re- connected by ?st disabling the aui port and then en- abling the aui port. the aui port on the primary eimr+ device defaults to enabled on reset. secondar y a ui p or t disab le si data 0010 1110 so data (pri) none so data (sec) none this command disables the aui port on the eimr+ de- vice designated as the secondary himib attachment. subsequently the eimr+ chip will ignore all inputs to this port and will not transmit a dat or jam pattern on the aui port. disabling the aui port also sets the parti- tioning state machine of the aui port to the idle state. therefore, a partitioned port can be reconnected by ?st disabling the aui port and then enabling the aui port. the aui port on the secondary eimr+ device defaults to enabled on reset. pr imar y a ui p or t enab le si 0011 1111 so data (pri) none so data (sec) none this command enables the aui port on the primary eimr+ device. secondar y a ui p or t enab le si data 0011 1110 so data (pri) none so data (sec) none this command enables the aui port on the eimr+ de- vice designated as the secondary himib attachment. when enabled, the secondary aui port is fully func- tional, and can be controlled by the serial/management interface. however, when used with the am79c987 de- vice, no status is displayed for this port since the himib device does not manage this port. at reset, this port is enabled. AM79C985 27 preliminary tp p or t disab le si data 0010 0### so data (pri) none so data (sec) none this command disables the tp port designated by the three least-signi?ant bits of the command byte. sub- sequently the eimr+ chip will ignore all inputs to the designated port and will not transmit a dat or jam pat- tern on that port. disabling the tp port also sets the partitioning state machine of that port to the idle state. therefore, a partitioned port can be reconnected by ?st disabling the port and then enabling it. designated port values of b111 through b100 in the command byte cor- respond to tp7 through tp4 in the primary eimr+ de- vice. designated port values of b011 through b000 in the command byte correspond to tp3 through tp0 in the secondary eimr+ device. tp p or t enab le si data 0011 0### so data (pri) none so data (sec) none this command enables the tp port designated by the three least-signi?ant bits of the command byte. desig- nated port values of b111 through b100 in the command byte correspond to tp7 through tp4 in the primary eimr+ device. designated port values of b011 through b000 in the command byte correspond to tp3 through tp0 in the secondary eimr+ device. disab le link t est function (per tp por t) si data 0100 0### so data (pri) none so data (sec) none this command disables the link test function of the tp port designated by the three least-signi?ant bits of the command data. as a consequence of this, the port will no longer be disconnected if it fails the link test. if a port has the link test disabled, reading the link test status indicates a ?ink pass? designated port values of b111 through b100 in the command byte correspond to tp7 through tp4 in the primary eimr+ device. des- ignated port values of b011 through b000 in the com- mand data correspond to tp3 through tp0 in the secondary eimr+ device. enab le link t est function (per tp por t) si data 0101 0### so data (pri) none so data (sec) none this command enables the link test function of the tp port designated by the three least-signi?ant bits of the command data. as a consequence of this, the port is disconnected if it fails the link test. designated port values of b111 through b100 in the command byte cor- respond to tp7 through tp4 in the primary eimr+ device. designated port values of b011 through b000 in the command data correspond to tp3 through tp0 in the secondary eimr+ device. disab le link pulse (p er tp p or t) si data 0100 1### so data (pri) none so data (sec) none this command disables the transmission of the link pulse on the tp port designated by the three least-sig- ni?ant bits of the command byte. designated port val- ues of b111 through b100 in the command byte correspond to tp7 through tp4 in the primary eimr+ device. designated port values of b011 through b000 in the command data correspond to tp3 through tp0 in the secondary eimr+ device. enab le link pulse (p er tp p or t) si data 0101 1### so data (pri) none so data (sec) none this command enables the transmission of the link pulse on the tp port designated by the three least-sig- ni?ant bits of the command byte. designated port val- ues of b111 through b100 in the command byte correspond to tp7 through tp4 in the primary eimr+ device. designated port values of b011 through b000 in the command byte correspond to tp3 through tp0 in the secondary eimr+ device. disab le a utomatic receiv er p olar ity re v ersal (p er tp p or t) si data 0110 0### so data (pri) none so data (sec) none this command disables the automatic receiver polar- ity reversal function for the tp port designated by the three least-signi?ant bits in the command byte. if this function is disabled on a tp port receiving with reversed polarity (due to a wiring error), the tp port will fail the link test due to the incorrect polarity of the received link pulses. designated port values of b111 through b100 in the command byte correspond to tp7 through tp4 in the primary eimr+ device. designated port val- ues of b011 through b000 in the command byte corre- spond to tp3 through tp0 in the secondary eimr+ device. the state of automatic polarity reversal function is set by si on reset. if si is high at the rising edge of rst , the eimr+ device disables automatic polarity reversal. if si is low at the rising edge of rst , the eimr+ device enables automatic polarity reversal. 28 AM79C985 preliminary enab le a utomatic receiv er p olar ity re v ersal (p er tp p or t) si data 0111 0### so data (pri) none so data (sec) none this command enables the automatic receiver polarity reversal function for the tp port designated by the three least-signi?ant bits in the command byte. if enabled in a tp port, the eimr+ chip will automatically invert the polarity of that port s receiver circuitry if the tp port is detected as having reversed polarity (due to wiring er- ror). after reversing the receiver polarity, the tp port could then receive subsequent (reverse polarity) packets correctly. designated port values of b111 through b100 in the command byte correspond to tp7 through tp4 in the primary eimr+ device. designated port values of b011 through b000 in the command byte correspond to tp3 through tp0 in the secondary eimr+ device. disab le receiv er extended distance mode (p er tp p or t) si data 0110 1### so data (pri) none so data (sec) none this command disables the receiver extended dis- tance mode and restores the rxd circuit of the trans- ceiver to normal squelch levels for the tp-port driver designated by the three least-signi?ant bits of the com- mand data. designated port values of b111 through b100 in the command byte correspond to tp7 through tp4 in the primary eimr+ device. designated port val- ues of b011 through b000 in the command byte corre- spond to tp3 through tp0 in the secondary eimr+ device. enab le receiv er extended distance mode (p er tp p or t) si data 0111 1### so data (pri) none so data (sec) none this command modi?s the rxd circuit of the trans- ceiver for the tp-port driver designated by the three least-signi?ant bits of the command data. the rxd squelch-threshold value is lowered to accommodate signal attenuation associated with lines longer than 100 meters. designated port values of b111 through b100 in the command byte correspond to tp7 through tp4 in the primary eimr+ device. designated port values of b011 through b000 in the command byte correspond to tp3 through tp0 in the secondary eimr+ device. at reset, receiver extended distance mode is disabled and the rxd circuit defaults to normal squelch-thresh- old values. disab le softw are ov err ide of leds (p er p or t - a ui and tp , global) si data 1001 #### so data (pri) none so data (sec) none this command disables software override of the port leds. individual leds and combinations of leds can be se- lected via the lower four bits of the command byte, as follows: #### p or t(s) aff ected 0000-0111 tp0 - tp7 1000 primary aui 1001 secondary aui 1010 both aui ports 1011 all tp ports 1100 all ports 1101 primary global 1110 secondary global 1111 all global following command execution, the attributes displayed on the leds will be determined by ldc 0-2 . software override of leds is disabled after reset. enab le softw are ov err ide of bank-a leds (p er p or t - a ui and tp , global) si data 1011 #### so data (pri) none so data (sec) none this command forces the leds in bank a to blink. in- dividual leds and combinations of leds can be select- ed via the lower four bits of the command byte, as follows: #### p or t(s) aff ected 0000-0111 tp0 - tp7 1000 primary aui 1001 secondary aui 1010 both aui ports 1011 all tp ports 1100 all ports 1101 primary global 1110 secondary global 1111 all global the designated led drivers(s) will switch between low and ?ff at the rate set by the software override blink rate command. enable software override of bank a leds references the blink rate last issued, and overrides any other attribute speci?d by ldc 0-2 . soft- ware override of leds is disabled after reset. AM79C985 29 preliminary enab le softw are ov err ide of bank-b leds (p er p or t - a ui and tp , global) si data 1100 #### so data (pri) none so data (sec) none this command forces the leds in bank b to blink. in- dividual leds and combinations of leds can be select- ed via the lower four bits of the command byte, as follows. #### p or t(s) aff ected 0000-0111 tp0 - tp7 1000 primary aui 1001 secondary aui 1010 both aui ports 1011 all tp ports 1100 all ports 1101 primary global 1110 secondary global the designated led drivers(s) will switch between low and ?ff at the rate set by the software override of led blink rate command. enable software override of bank b leds references the blink rate last issued, and overrides any other attribute speci?d by ldc 0-2 . software override of leds is disabled after reset. softw are ov err ide of led blink rate si data 1110 1### so data (pri) none so data (sec) none this command sets the blink period of the leds with software override enabled. the duty cycle is 50%. this command defaults to ?ff at reset. setting blink p er iod 1110 1000 off 1110 1001 512 ms 1110 1010 1560 ms 1110 1011 solid on these settings apply to the blink rate for both bank a and bank b. this command must precede the enable software override of bank a/b leds command. all led combinations selected for software override will refer- ence the blink rate last issued. get (read commands) a ui p or t(s) status si data 1000 1111 so data (sec) pbsl p pbsl s so data (pri) 0000 pbsl so data (single) pbsl 0000 the combined aui status of the eimr+ device(s) allows a single instruction to be used to monitor the aui port(s). the four local status bits are: p partitioning status this bit is ? if the aui port is partitioned and ? if the aui port is connected. b bit rate error this bit is set to ? if there is an instance of fifo over- ?w or under?w. the bit is cleared when the eimr+ device is read. s sqe test status this bit is set to ? if the sqe test error is detected by the eimr+ chip. the bit is cleared when the status is read. l loopback error the mau attached to the aui port is required to loop- back data transmitted to do onto the di circuit. if the loopback carrier is not detected by the eimr+ device, this bit is set to ?? this bit is cleared when the status is read. if a single eimr+ device is connected to a himib device, so is pbsl 0000. if two eimr+ devices are connected to a himib device, so on the primary device is 0000 pbsl p , and so on the secondary device is pbsl p pbsl s . the subscript ( p ) indicates the statistics of the primary eimr+ device and the subscript ( s ) indicates the statistics of the secondary eimr+ device. alter nate a ui p or t(s) status there are three further variations of the aui port status command allowing selective clearing of a combination of b,s, and l bits. these are the following: alternate 1: b is not cleared, s and l are cleared si data 1000 1011 so data (sec) pbsl p pbsl s so data (pri) 0000 pbsl so data (single) pbsl 0000 alternate 2: s and l are not cleared, b is cleared si data 1000 1101 so data (sec) pbsl p pbsl s so data (pri) 0000 pbsl so data (single) pbsl 0000 alternate 3: none of s, b, and l are cleared si data 1000 1001 so data (sec) pbsl p pbsl s so data (pri) 0000 pbsl so data (single) pbsl 0000 30 AM79C985 preliminary tp p or t p ar titioning status si data 1000 0000 so data (sec) 0000 p3..p0, p7..p0 (output to himib) so data (pri) 0000 p7..p4 so data (single) 0000 p3..p0 p n = 0 tp port partitioned p n = 1 tp port connected where n is a port number in the range 0-7 the response to this command gives the partitioning status of all four tp ports. if a port is disabled, reading its partitioning status will indicate that it is connected. if two eimr+ devices are connected together, the second- ary device indicates the status of all eight tp ports. p7...p4 correspond to the four ports of the primary device. p3..p0 correspond to the four ports of the sec- ondary device. bit rate error status of tp p or ts si data 1010 0000 so data (sec) 0000 e3..e0, e7..e0 (output to himib) so data (pri) 0000 e7..e4 so data (single) 0000 e3..e0 e n = 0 no error e n = 1 fifo over?w where n is a port number in the range 0-7. the response to this command gives the bit-rate-over- ?w or under?w (data rate mismatch) condition of all the tp ports. a 1 indicates that the fifo has over?wed or under?wed due to the amount of data received by the corresponding port. if two eimr+ devices are con- nected together, the secondary device indicates the sta- tus of all eight tp ports. e7...e4 correspond to the four ports of the primary device. e3...e0 correspond to the four ports of the secondary device. link t est status of tp por ts si data 1101 0000 so data (sec) 0000 l3..l0, l7......l0 (output to himib) so data (pri) 0000 l7..l4 so data (single) 0000 l3..l0 l n = 0 tp port n in link test failed l n = 1 tp port n in link test passed where n is a port number in the range 0-7. the response to this command gives the link test sta- tus of all the tp ports. a disabled port continues to report link test status. re-enabling the port causes the port to be placed in the link test fail state. if two eimr+ devices are connected together, the secondary device indicates the status of all eight tp ports. l7..l4 corre- spond to the four ports of the primary device. l3..l0 correspond to the four ports of the secondary device. receiv e p olar ity status of tp p or ts si data 1110 0000 so data (sec) 0000 p3......p0, p7.....p0 (output to himib) so data (pri) 0000 p7......p4 so data (single) 0000 p3......p0 p n = 0 tp port n polarity correct p n = 1 tp port n polarity reversed where n is a port number in the range 0-7 the response to this command gives the received po- larity status of all the tp ports. if the polarity is detected as reversed for a tp port, then the eimr+ device will set the appropriate bit in this command s result only if the polarity reversal function is enabled for that port. if two eimr+ devices are connected together, the secondary device indicates the status of all eight tp ports. p7...p4 correspond to the four ports of the primary device. p3..p0 correspond to the four ports of the sec- ondary device. mjlp status si data 1111 0000 so data (sec) m000 0000, m p 000 m s 000 (to himib) so data (pri) 0000 m000 so data (single) m000 0000 each eimr+ device contains an independent mau jab- ber lock up protection timer. the timer is designed to inhibit the transmit function of the eimr+ device if it has been transmitting continuously for more than 65536 bit times. this bit remains set and is only cleared when the mjlp status is read using this command. if two eimr+ devices are connected together, the secondary device will indicate the status of both devices (m p is the status of the primary device; m s is the status of the secondary device). v ersion si data 1111 1111 so data (sec) 0000 0011, 0011 p 0011 s (to himib) so data (pri) 0000 0011 so data (single) 0000 0011 the response to this command gives the version of the eimr+ device. 0011 was chosen to help distinguish the eimr+ device from the imr (am79c980) and the imr+ (am79c981) devices. if two eimr+ devices are con- nected together, the secondary device will indicate the version of the primary device in the upper four bits of the so byte, and its own version number in the lower four bits. AM79C985 31 preliminary systems applications eimr+ to tp port connection the eimr+ device provides a system solution to designing non-managed multiport repeaters. the eimr+ device connects directly to ac coupling mod- ules for a 10base-t hub. figure 9 shows the simpli- ?d connection. twisted pair transmitters txd signals need to be properly terminated to meet the electrical requirement for 10base-t transmitters. proper termination is shown in figure 10 which consists of a 110- w resistor and a 1:1 transformer. the load is a twisted- pair cable that meets ieee 802.3, section 14.4 speci?ations. the cable is terminated at the opposite end by 100 w . twisted pair receivers rxd signals need to be properly terminated to meet the electrical requirements for 10base-t receivers. proper termination is shown in figure 11. note that the receivers do not require external ?ter modules. figure 9. simpli?d 10base-t connection figure 10. txd termination 110 100 110 100 110 100 110 100 tp connector tp connector tp connector tp connector eimr+ txd0+ txd0 rxd0+ rxd0 txd1+ txd1 rxd1+ rxd1 txd2+ txd2 rxd2+ rxd2 txd3+ txd3 rxd3+ rxd3 rst clk 1:1 1:1 1:1 1:1 1:1 1:1 1:1 1:1 20651b-14 20651b-15 1:1 twisted pair 100 110 txd+ txd- 20650a-13 32 AM79C985 preliminary figure 11. rxd termination mac interface the eimr+ device can be connected directly to a mac through the aui port. this requires that the aui port be con gured in the reverse mode and connected as shown in figure 12a. notice that di is connected to do of the mac and do is connected to di of the mac, be- cause the reverse con?uration only affects ci. where ci is an input in the normal mode, in the reverse mode, ci is an output. figure 12b shows the normal aui con- ?uration for reference. figure 12. aui port interconnections internal arbitration mode connection the internal arbitration mode uses a modi?d daisy- chain scheme to eliminate the need for any external arbiter. in this mode, a ck and col need to be pulled up through a minimum resistance of 1 k w. the dat and jam pins also need to be pulled down via a high value resistor. refer to figure 13. imr+ mode external arbitration the imr+ mode maintains the full functionality of amd s imr+ (am79c981) device s expansion bus. in this mode, the eimr+ device requires external circuitry to handle arbitration for control of the bus. figure 14 shows the con?uration for the imr+ mode of operation. 20650a-14 1:1 twisted pair 100 100 rxd+ rxd 20650a-14 20651b-16 do+ do di+ di ci+ ci di+ di do+ do ci+ ci di+ di do+ do ci+ ci di+ di do+ do ci+ ci a) reverse mode (with mac) b) normal mode (with mau) am79c940 eimr+ am7996 eimr+ 0.1 f 0.1 f 0.1 f 0.1 f 39 ?150 0.1 f 40 40 40 40 40 40 40 40 40 40 40 40 ? v 1:1 1:1 1:1 20651a-17 20651b-17 AM79C985 33 preliminary figure 13. eimr+ internal arbitration mode connection figure 14. imr+ mode external arbitration v dd v dd v dd ~1 k w 1 k w ~1 k w d q q p c d q q p c rst 74ls74 20 mhz osc clk dat jam ack col clk dat jam ack col ( note: in a multiple eimr+ system, the reset signal must be synchronized to clk.) clk dat jam ack col eimr+ seli_0 seli_1 rst selo eimr+ seli_0 seli_1 rst selo eimr+ seli_0 seli_1 rst selo 20651b-18 seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col col ack sel1 sel2 sel3 arbiter gcol eimr+ eimr+ eimr+ 1 k w seli_0 seli_1 selo dat jam ack col 20651b-19 34 AM79C985 preliminary visual status display lda/b[4:0] and ldga/b provide visual status indicators for the eimr+. lda/b[4:0] displays link, carrier sense, collision, and partition information for the tp and aui ports. ldga/b display global carrier sense, collision, and jabber information. in a multiple eimr+ con?uration, the global led driv- ers (ldga/b) from each chip can be tied together to drive a single pair of global status leds. the open drain output of these drivers facilitate this con?uration. refer to figure 15. figure 15. visual status display connection lda[4:0] ldb[4:0] ldga ldgb lda[4:0] ldb[4:0] ldga ldgb eimr+ eimr+ vdd 20651b-20 AM79C985 35 preliminary absolute maximum ratings storage temperature . . . . . . . . . . ?5 c to +150 c ambient temperature under bias . . . . 0 c to +70 c supply voltage referenced to av ss or dv ss (av dd , dv dd ) . . . . . . . ?.3 v to +6.0 v stresses above those listed under absolute maxi- mum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect reliability. programming conditions may differ. operating ranges commercial (c) devices temperature (t a ) . . . . . . . . . . . . . . . . . 0 c to +70 c supply voltages (v dd ) . . . . . . . . . . . . . . . . .+5 v 5% operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise speci?d parameter symbol parameter description test conditions min max unit digital i/o v il input low voltage v ss = 0.0 v ?.5 0.8 v v ih input high voltage v ss = 0.0 v 2.0 0.5 + v dd v v ol output low voltage i ol = 4.0 ma 0.4 v v oh output high voltage i oh = ?.4 ma 2.4 v i il input leakage current v ss 38 AM79C985 preliminary switching characteristics (continued) notes: 1. parameter not tested. 2. di pulses narrower than t pwodi (min) will be rejected; pulses wider than t pwodi (max) will turn internal di carrier sense on. 3. di pulses narrower than t pwkdi (min) will maintain internal di carrier on; pulses wider than t pwkdi (max) will turn internal di carrier sense off. 4. ci pulses narrower than t pwoci (min) will be rejected; pulses wider than t pwoci (max) will turn internal ci carrier sense on. 5. ci pulses narrower than t pwkci (min) will maintain internal ci carrier on; pulses wider than t pwkci (max) will turn internal ci carrier sense off. 6. rxd pulses narrower than t pwkrd (min) will maintain internal rxd carrier sense on; a pulse wider than t pwkrd (max) will turn rxd carrier sense off. parameter symbol parameter description test conditions min max unit twisted pair port timing t txtd clk rising edge to txd transition delay 50 ns t tetd transmit end of transmission 250 375 ns t pwkrd rxd pulse width maintain/turn-off threshold |v in |>|v ths | (note 6) 136 200 ns t perlp idle signal period 8 24 ms t pwlp idle link test pulse width 75 120 ns management port timing t sclk sclk clock period 100 ns t sclkh sclk clock high 30 ns t sclkl sclk clock low 30 ns t sclkr sclk clock rise time 10 ns t sclkf sclk clock fall time 10 ns t siset si input setup time to sclk rising edge 10 ns t sihld si input hold time from sclk rising edge 10 ns t sodly so output delay from sclk rising edge c l = 100 pf 40 ns t clkhcrs clk rising edge to crs valid c l = 100 pf 5 40 ns t strset str setup time 5 ns t strhld str hold time 9 ns AM79C985 39 preliminary key to switching waveforms switching waveforms figure 16. clock timing must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010-pal t clk t clkh t clkl t clkr t clkf clk 20650a-20 20651b-21 40 AM79C985 preliminary switching waveforms (continued) figure 17. management port timing figure 18. reset timing figure 19. mode initialization t sclkh t sclkl t sodly t sclk t siset t sihld sclk si/si_d so t sclkf t sclkr 20651b-22 note: tclk represents internal eimr+ timing t rst or t prst t rsthld t rstset clk rst tclk 20651b-23 t xrs t xrh amode, seli[0], si_d, crs_i rst 20651b-24 AM79C985 41 preliminary switching waveforms (continued) figure 20. expansion bus input timing figure 21. expansion bus output timing note: tclk represents internal eimr+ timing clk tclk selo ack col dat/jam t djset t djhold in 20651b-25 clk tclk selo ack col dat/jam t clkhrh t caset t caset t clkhrl t cahld t clkhdr t clkhdz out note: tclk represents internal eimr+ timing 20651b-26 42 AM79C985 preliminary switching waveforms (continued) figure 22. expansion bus collision timing figure 23. aui timing diagram figure 24. aui receive diagram 20651a-27 clk tclk selo ack col dat/jam t clkhrh t clkhrl t caset t caset t cahld in in note: tclk represents internal eimr+ timing 20651a-27 20651b-27 clk d0+ d0- t dotd t dotr t dotf t doetd 20651b-28 20651b-29 t pwkdi v asq (t pwkci ) t pwodi (t pwoci ) t pwkdi (t pwkci ) di+ (ci ) 20650a-28 AM79C985 43 preliminary switching waveforms (continued) figure 25. tp ports output timing diagram figure 26. tp idle link test pulse figure 27. tp receive timing diagram txd+ 10111010etd txd 0 1 t tetd clk t txtd 20651b-30 t pwlp t perlp 20651b-31 rxd+/ v tsq t pwkrd v tsq+ t pwkrd v ths+ v ths t pwkrd 20560a-31 20651b-32 44 AM79C985 preliminary switching test circuit figure 28. switching test circuit pin test point v dd v ss 20650a-32 20651b-33 AM79C985 45 preliminary physical dimensions pl 084 84-pin plastic leaded chip carrier (measured in inches) top view seating plane 1.185 1.195 1.150 1.156 pin 1 i.d. .026 .032 .050 ref .042 .056 .062 .083 .013 .021 1.000 ref .007 .013 .165 .180 .090 .130 16-038-sq pl 084 df79 8-1-95 ae side view 1.185 1.195 1.150 1.156 1.090 1.130 46 AM79C985 preliminary pqr100 100-pin plastic quad flat pack pin 100 pin 50 pin 30 pin 1 i.d. 17.00 17.40 12.35 ref 13.90 14.10 18.85 ref 19.90 20.10 23.00 23.40 0.25 min 2.70 2.90 0.65 basic 3.35 max seating plane 16-038-pqr-1_ah pqr100 dp92 6-20-96 lv pin 80 AM79C985 a-1 appendix a security eavesdrop protection the eimr+/himib devices are capable of providing network eavesdrop protection. this feature is protected by a software key. an application note containing the necessary software key and implementation details is available from amd. a brief description of eavesdrop protection is given below. for more information, contact your local amd sales representative. features summary eavesdrop protection is based on the concept that con- ?ential data should only be received by speci?d se- cure stations. the eimr+/himib devices are capable of repeating packets only to ports considered secure for a packet s destination address. on all other ports, trans- mission can be disrupted by transmitting a pattern of alternating 1s and 0s. the eimr+/himib can disrupt packet transmission, as described above, on ports not having a valid address. valid addresses are determined by comparing a packet s destination address with the two address reg- isters associated with each repeater port: last source address register and preferred source address reg- ister. eavesdrop protection can be masked on a port- by-port basis. disruption of multicast packets can also be masked on a port-by-port basis. if the destination address is a broadcast address, the packet is transmit- ted unmodi?d on all ports. in many instances, a station targeted with a speci? destination address will not reside within the same re- peater as the originating station. to ensure that packets arrive at the intended destination, eimr+/himib ports can be programmed to pass packets with an invalid des- tination address undisturbed if no other port on the re- peater has a valid address that matches the destination address. the eimr+/himib devices can determine if there is a match on the repeater by monitoring its ports and by monitoring signals on the eimr+/himib expan- sion bus. figure a1. str input signal from am79c987 himib device aui tp0 tp1 tp2 tp3 tp4 tp5 tp6 tp7 clk tclk str note: tclk illustrates internal eimr+ chip clock phase relationship. 20651b-34 a-2 AM79C985 trademarks copyright 1997 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. hardware implemented management information base (himib), integrated multiport repeater (imr) integrated multiport repeater plu s (imr+), basic integrated multiport repeater (bimr), and enhanced multiport repeater plus (eimr+) are trademarks of advanced micro devic es, inc. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies. |
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